As semiconductor devices have evolved to have high performance and to become highly integrated, development of what is called “All Digital Phase-Locked Loop (ADPLL)” progresses, which is a phase synchronization circuit configured with a digital circuit as a whole. Compared with a conventional analog PLL circuit, an ADPLL circuit has, for example, advantages such as low-voltage operation, compatibility with fine process, and the like. An ADPLL circuit can be used for, for example, a frequency synthesizer for a wireless communication circuit as well as a clock generator for an arithmetic circuit or an interface circuit.
A clock generator in general generates a faster clock from an input clock that has a reference frequency FREF. In a clock generator based on an ADPLL circuit, this multiplication number is given by a digital input value called a “Frequency Command Word (FCW)” or the like. Therefore, if a given input clock and an FCW are input, an output clock has, as illustrated in FIG. 1, a time-invariant frequency FREF*FCW (FIG. 1A), and an acute electric field peak at that frequency (FIG. 1B). However, such an output spectrum peak generates unnecessary electromagnetic interference (EMI) from a circuit and/or an electronic device including the clock generator. As EMI exerts an influence on peripheral devices, it is restricted by various standards. For example, EMI is often restricted for various interface circuits that execute high-speed data exchange between devices.
As a technology that can suppress EMI, a spread spectrum clock generator (SSCG) is known. An SSCG can suppress an electric field peak, as illustrated in FIGS. 2A-2B, by slightly fluctuating the frequency of an output clock to oscillate for spreading the output spectrum (FIG. 2A), with the same total power (FIG. 2B). Here, in FIG. 2B, an electric field curve without spread spectrum illustrated in FIG. 1B is illustrated with a dashed line for comparison. Therefore, unnecessary radiation from a circuit and/or an electronic device including an SSCG can be suppressed, which in turn can suppress or avoid an adverse influence to peripheral devices and the like.
An SSCG fluctuates an output frequency, in general, with a triangular waveform as illustrated in FIG. 2A to obtain a flatter output spectrum waveform. A value obtained with the spread width ΔFout (peak-to-peak value) of an output frequency divided by the reference value (FREF*FCW) of the output frequency is called a spread ration, and the frequency of a triangular wave is called a spread frequency FSS. For example, a spread ratio can be set to 0.5% to 5%, and a spread frequency can be set to several kHz to several hundred kHz. Here, in FIG. 2A, a case of what is called a “down-spread” method is illustrated that sets FREF*FCW as a maximum value of the output frequency having a triangular waveform. Alternatively, what is called a “center-spread” method may be used that sets FREF*FCW as a center value of the output frequency.
An ADPLL circuit typically includes a phase comparison circuit, a low-pass filter, also called as a loop filter, and a digitally controlled oscillator (DCO). In addition to theses ADPLL circuit configuration elements, an SSCG based on ADPLL includes a triangular wave generating circuit for spectrum spreading, and can be classified into two methods depending on a connect position of the triangular wave generating circuit. A first method adds the triangular wave to the frequency command word (multiplication number setting value) FCW input to a phase comparison circuit, and a second method adds the triangular wave to the output of the loop filter that becomes the input code for the DCO.
In the first method, the triangular wave is directly added to the frequency command word, hence it is possible to achieve a desired spread ration (even if gain compensation of the DCO is incomplete, which will be described later). However, the spread frequency needs to be contained in a band of the closed loop function (low-pass characteristic) of a PLL circuit between the triangular wave is added to the input of the PLL circuit, and phase information including a triangular wave component needs to be transmitted to the DCO via the loop filter. If the spread frequency is set outside of the band, the triangular wave attenuates. On the contrary, in the second method, the spread frequency needs to be set outside of the band of the closed loop function of the PLL circuit. From the DCO input viewpiont, the transfer function has a high-pass characteristic, with which the triangular wave attenuates if the spread frequency is set in the band of the closed loop function. In the following, for the sake of explanation, SSCGs according to the first and second methods above will be referred to as a “slow SSCG” and a “fast SSCG”, respectively, based on the spread frequency range that can be set.
FIG. 3 schematically illustrates the Spread frequency range that can be set with a slow SSCG and a fast SSCG. fc is the cutoff frequency of the closed loop function of a PLL circuit. The cutoff frequency fc has a restriction, which usually makes it be set to under 1/10 of the input clock frequency FREF, for example, between 1/100 and 1/10. If the spread frequency is close to fc, waveform distortion may occur, hence the spread frequency in the slow SSCG is restricted within a frequency range that is further lower than fc. In contrast, it is possible for the fast SSCG to spread a spectrum at a comparatively high frequency. A high spread frequency can reduce data amount that needs to be buffered between a circuit that operates with a clock generator without using a spread spectrum and a circuit that operates using an SSCG. Therefore, a fast SSCG is often required for various circuits such as various interface circuits and the like.
However, the following problem may arise with a typical fast SSCG in which the triangular wave is added to an input code for a DCO. A DCO outputs a clock with an oscillation frequency that corresponds to the digital input code, and usually sets a frequency change amount per input code Δf to a desired value fd (Δf=fd[Hz/one code]). This slope of the DCO is called gain or KDCO as well. As KDCO varies with an element variation of semiconductor manufacturing, a multiplier is placed at the DCO input to multiply a gain compensation coefficient cor_GAIN to make Δf=cor_GAIN*KDCO=fd[Hz/1code]. If the gain compensation coefficient cor_GAIN is not appropriate, for example, if KDCO after compensation deviates 20 to 30%, it is not a major problem with a usual PLL although a closed-loop characteristic may deviate a bit. However, with a fast SSCG, a deviation for cor_GAIN directly lead to a deviation of the spread ration.
FIG. 4 schematically illustrates a generation of spread ration deviation caused by such deviation of cor_GAIN. Assuming that a required value of cor_GAIN is k, and if it is exactly that cor_GAIN=k, the frequency increment amount per code becomes Δf=fd. If the target value of the spread ratio is 5%, the actually obtained spread ratio becomes 5%. However, for example, if it is set that cor_GAIN=0.8*k, the frequency increment amount per code becomes Δf=0.8*fd. If the target value of the spread ratio is 5%, the actually obtained spread ratio becomes 5*0.8=4%, which deviates from the target value. Of course, if it is set that cor_GAIN>k, a spread ratio over the target value is obtained.
Such deviation of the spread ratio from the target value changes a reduction amount of the electric field peak illustrated in FIG. 2B. Especially, if an actual spread ratio is smaller than the target value, there may be cases in which a desired EMI suppressing effect is not obtained. Also, especially, with the down-spread method of spectrum spreading, if an actual spread ratio is greater than the target value, an unexpected situation may arise in which the maximum clock frequency exceeds FREF*FCW. An excessive clock frequency may be a cause for collapse of timing design of a digital circuit including such an SSCG.
[Related-Art Documents]
[Patent Documents]
[Patent Document 1] Japanese Laid-open Patent Publication No. 2009-177685
[Patent Document 2] Japanese Laid-open Patent Publication No. 2009-21954